Abstract
Detailed simulations of processor networks based on the Scalable Coherent Interface (SCI) show that SCI is suitable as a data carrier in data acquisition systems where the total bandwidth need is in the multi GBytes/s range and a low latency is required. The objective of these simulations was to find topologies with low latency and high bandwidth, but also with the cost of implementation in mind. A ring-to-ring bridge has been used as the building element for the networks. The simulations have been performed on regular k-ary n-cube type topologies from a few tens of nodes and up to about 500 nodes under different load conditions. Among the parameters which have been manipulated in the simulations are the number of nodes, topology structure, number of outstanding requests and load in the system
