Abstract
This paper investigates the power cycling methodology for reliability testing of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). Dedicated test benches were designed and built to study this issue. The results indicate that power cycling of SiC MOSFETs is affected by threshold voltage instability. A proposal for reducing the influence of the latter is also given. This is done by adding an additional gate pulse to the device under test, in order to achieve an average bias of zero during one cycle of the power cycling experiment.
