Abstract
The electrical effects of anodic bonding on the gate oxide of packaged
MOS devices are presented, and shown to be dependent both on the gate
oxide fabrication process and on the design of the glass cavity. We
propose methods to incorporate these effects in the device models to
ensure reliable circuit simulations for the wafer-level packaged
devices.
MOS devices are presented, and shown to be dependent both on the gate
oxide fabrication process and on the design of the glass cavity. We
propose methods to incorporate these effects in the device models to
ensure reliable circuit simulations for the wafer-level packaged
devices.
